Multi-processor systems have a set of processors interconnected across a local or distributed network. The local network may be contained within a single computer and the distributed network may be part of a local area network, wide area network, or others. Each processor may be interconnected with other processors on a single processor bus or connected to a local bus separate from other processor buses. Interconnected processors may be grouped in clusters. Each cluster can be connected to a processor bus and routed to a system memory via a system memory controller or a bus bridge.
Processors in multi-processor systems include hierarchical inclusive caches in which higher level caches store the same cache lines stored in lower level caches in addition to other cache lines. The lower level caches are closer to the execution units of a processor and have a relatively fast access time and relatively lower storage capacity in comparison to a higher level cache. Due to inclusivity of all cache lines in the lower level cache within the higher level cache, only the higher level cache monitors commands on the system bus. The monitoring is termed snooping. A cache snoops a command by comparing addresses associated with snooped commands to cache line addresses. If the addresses match, the cache updates a memory coherency image state for the cache line and sends a snoop response based on the updated memory coherency image state. If no match is found, the cache sends a snoop response indicative of the condition.
Snoop responses in multiple-processor systems are typically handled by exposing each processor core to a system bus and increasing the number of hit and hit-modified (hitm) snoop lines which are wire ORed together. Accordingly, each processor core drives associated snoop responses to the bus, potentially causing compatibility problems when single-core and dual-core systems are combined.